1. Field of the Invention
This invention is directed to very thin gate oxide semiconductor devices having source, drain and channel regions all doped with dopants of the same conductivity type, and to complementary devices in which the three regions of one device are all of the same conductivity type, but opposite to the conductivity type of the three regions of the other device.
2. Background Information
Conventional complementary metal oxide silicon (CMOS) transistors have source and drain regions of the same conductivity type with a channel region between of the opposite conductivity type. Thus, one transistor is a npn device and the complementary transistor is a pnp type. These devices have a threshold voltage which is typically about 500 to 1500 millivolts. Furthermore, the capacitance of such devices is high due in part to an oxide layer of about 100 to 500 Angstroms (.ANG.) in thickness insulating the gate electrode from the channel region. Since the power required by these devices and their switching speed are both direct functions of the capacitance and threshold voltage, they are relatively power hungry and slow for certain applications.
One such application is an interface between high temperature superconducting (HTSC) circuits, typically operating at 77.degree. K, and conventional silicon devices operating at ambient conditions (300.degree. K). The HTSC circuits potentially have P * Tau (power-delay) product capabilities as low as the 1E-17 to the 1E-16 joule level. Because of the relatively high threshold voltages and slow response times of conventional silicon NPN/PNP logic families, they themselves do not approach such power-delay products, and hence, are a poor match to serve as glue circuits for the HTSC families.
There is a need therefore, in general, for higher speed, significantly lower power semiconductor devices, and there is a particular need for such a device which can serve for instance as an interface between HSTC circuits and ambient silicon devices.
In this connection, there is a need for improved semiconductor devices which have lower threshold voltages, and particularly well below about the 100 millivolt level.